Analog to digital (A/D) converters, which are used to convert analog signals into digital form, are used in numerous electronic applications such as audio and video recording, telecommunications systems and sensing systems. Depending on the particular application and its corresponding specifications, such as sampling rate, resolution and linearity, different A/D architectures are suitable for various applications. For example, low power medium resolution A/Ds are used for applications such as ultrasound and analog front ends for digital cameras.
In moderate sampling rate applications with medium resolution requirements, for example, sampling rates between 10kΩ and 10MΩ, and bit resolutions of between 8 bits and 11 bits, successive approximation A/D converters are pervasive. A successive approximation A/D, as shown in FIG. 1, has comparator 106, successive approximation register and control logic 104, DAC 102 and summing circuit 108. To perform a conversion, DAC 102 is set to half of full-scale with a code, for example, of 10000000 (binary). Comparator 106 compares the difference between the output of DAC 102 and input voltage V1 to determine the most significant bit (MSB) of the digital output word. If the output of DAC 102 is greater than Vi, the DAC is set to one-quarter scale (i.e., 01000000) during a next comparison cycle. If, on the other hand, the output of DAC 102 is less than Vi, the DAC is set to three-quarter scale (i.e., 11000000) during the next conversion. During the next conversion, the difference between the output of DAC 102 input voltage Vi is again compared to determine the next DAC value. The output of DAC 102 gradually approximates input voltage Vi more and more during each successive cycle. After eight comparison cycles, a digital output code is determined based on the input to DAC 102.
FIG. 2 illustrates a conventional switched capacitor implementation 200 of a successive approximation A/D. The switched capacitor successive approximation A/D converter has comparator 204, and register and switch control logic 202. The DAC is implemented with binary weighted capacitor array 210 and switches 208. Capacitor array 210 is also used as a sampling capacitor. During a first phase of operation, input Vi is coupled to the bottom plates of capacitor array 210 via switches 208, and the top plates of capacitor array 210 is coupled to ground via switch 206. Switch 206 is then opened, the bottom plates of capacitor array 210 remain coupled to Vi, and a first comparison is made. The bottom plate of capacitor group 210 is then coupled to Vref+ or Vref− depending on the result of the previous comparison. After each conversion cycle, each successive capacitor group is successively coupled to Vref+ or Vref− until the binary search is complete and an output code is derived. Because charge is conserved in capacitor array 210, errors do not accumulate after each conversion cycle. For high resolutions, however, A/D linearity and accuracy can be compromised because if comparator 204 is slow or inaccurate. Practical implementations of a switched capacitor successive approximation A/D converter 200, may, therefore use very high power comparators.